Generate Aurora 64B/66B Core IP - 2023.2 English

Now let us generate the Aurora IP. To illustrate the IP configuration options clearly, use AMD Vivado™ GUI to see the graphical Aurora IP configuration options with U200 card as an example.

Start the Vivado GUI. In the Tcl Console window, enter the following example command to create a project using the FPGA part corresponding to your Alveo card. In the following command line, xcu200-fsgd2104-2-e is the FPGA part name of U200 card.

create_project aurora_test -part xcu200-fsgd2104-2-e

After the project is created, click IP Catalog in the PROJECT MANAGER on the left, find Aurora 64B66B IP in the list, and double click it. Once done, the Aurora 64B66B IP configuration window pops up, and review and make necessary changes to the options as explained below.

We configure the Core Options tab as below:

• Physical Layer

  • GT Type: GTY (default)

  • Line Rate (Gbps): 10.3125 (default)

  • Column Used: Right (default)

  • Lanes: 4 (the example design uses four lanes)

  • Starting GT Quad: Quad X1Y5 (default, the Vitis linking process will choose the correct GT Quad)

  • Starting GT Lane: X1Y20 (default, the Vitis linking process will choose the correct GT Lane)

  • GT Refclk Selection: MGTREFCLK0 of Quad X1Y5 (default, the Vitis linking process will choose the correct GT Refclk)

  • GT Refclk (MHz): 161.1328125 (This matches the GT clock source on the Alveo card)

  • INIT clk (MHz): 100 (use the 100MHz clock provided in the U200 target platform as the INIT clk)

  • Generate Aurora without GT: Keep unselected (you need the Aurora IP to include the GT transceiver)

• Link Layer

  • Dataflow Mode: Duplex (default)

  • Interface: Streaming (used in the example design)

  • Flow Control: None (default)

  • USER K: Keep unselected (do not use USER-K in the example design)

  • Little Endian Support: Keep unselected (little endian support in the example design is not required)

• Error Detection

  • CRC: Keep unselected (CRC in the example design is not needed)

• Debug and Control

  • DRP Mode: Native ( DRP function is not used in the example design)

  • Vivado Lab Tools: Keep unselected (this feature is not used in the example design)

  • Additional transceiver control and status ports: Keep unselected (this feature is not used in the example design)

We configure the Shared Logic tab as below:

• Shared Logic

  • Include Shared Logic in core (single Aurora module is used in the example design)

Following above settings, the Aurora 64B66B IP configuration window is as below:

The configured IP will have an AXI stream slave port and an AXI stream master port, and the data width is 256 bits, namely 64 bits per lane. These two AXI stream ports work on 161.1328125 MHz user_clk domain, which is 1/64 of 10.3125 Gbps lane speed.

After clicking OK button, the Aurora IP configuration is finished. You need the generated aurora_64b66b_0.xci file, which is used later in the IP package step. As mentioned earlier, the Aurora IP generation step is finished by the Vivado Tcl script in this tutorial. So let us look at the script file ./tcl/gen_aurora_ip.tcl, which is used to generate the same output as above GUI flow. The major part of this script is as below:

create_ip -name aurora_64b66b \
          -vendor xilinx.com \
          -library ip \
          -version 12.0 \
          -module_name aurora_64b66b_0 \
          -dir ./ip_generation

set_property -dict [list CONFIG.C_AURORA_LANES {4} \
                         CONFIG.C_LINE_RATE {10.3125} \
                         CONFIG.C_REFCLK_FREQUENCY {161.1328125} \
                         CONFIG.C_INIT_CLK {100} \
                         CONFIG.interface_mode {Streaming} \
                         CONFIG.drp_mode {Native} \
                         CONFIG.SupportLevel {1}] \
             [get_ips aurora_64b66b_0]

With the script, you can use following command line to generate the Aurora IP (u200 card as example):

vivado -mode batch -source ./tcl/pack_kernel.tcl -tclargs xcu200-fsgd2104-2-e

Because a Makefile is provided to manage the full flow, use the make command to finish all the steps.