A Makefile is provided here to run the simulation. Use following command to run the Verilog simulation:
cd ~/aes
make runsim
The simulation is executed with 256 input words (128-bit) along with pre-defined KEY. You can modify the simulation options in the ~/aes/runsim_aes_xsim.sh file. After simulation finishes, a waveform dump file called work.tb_aes.wdb is generated, in which you can view the interface waveform. The following image shows an example interface waveform.
Now that you have the necessary information about the Aes module, you can start to add the necessary AXI interfaces and IPs to make it a usable kernel for the Vitis flow. This is described in the next section: RTL Kernel: krnl_aes.
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