Vitis Tutorials: Vitis Platform Creation - 2023.1 English

Document ID: XD101
Release Date: 2023-08-02
Version: 2023.1 English

Vitis Tutorials: Vitis Platform Creation
Design Tutorials
Feature Tutorials
Design Tutorials
Versal Platform Creation Quick Start
Step 1: Create Vivado Design and Generate XSA
Step 2: Create Vitis Platform
Step 3: Validate this Vitis PLatform
Run the Application on Hardware
Fast Track
Create a Vitis Platform for Custom Versal Boards
Step 1: Create a Hardware Platform for Customer's VCK190
Create the Vivado Project
Configure the Block
Add the Constraint File
Review the Versal Extensible Platform Example Part_base Platform Setup
Review the Simulation Model
Export Hardware XSA
Validate the Output of Step 1
Fast Track
Next Step
Step 2: Create Vitis Software Platform
Prepare the Common Images
Create the Device Tree File
Create the Vitis Platform
Validate the Output of Step 2
Fast Track
Next Step
Step 3: Run Application on the Platform
Application 1: Run a PL Acceleration Application
(Optional) Test the Application on Hardware Emulation
Test the Application on Hardware
Application 2: Run an AIE + PL Acceleration Application Project
Test the Application on Hardware
(Optional) Test the Application on Hardware Emulation
Frequently Asked Questions
Why can’t my platform boot on hardware?
Why can’t my platform boot on hardware emulation?
Why can’t my platform support hardware emulation?
PLM IPI Issue
When is the AIE app and PL kernel being programmed?
Why does my AIE system application hang?
Versal DFX Platform Creation Tutorial
Step 1: Create the Hardware Design
Step 1: Create the Hardware Design
Vivado Design Creation
Project Creation
DFX Platform Design Submodule Explanation
Memory Subsystem
Control Subsystem
AI Engine Subsystem
Interrupt Subsystem
Clock and Reset
Export Hardware Emulation XSA
Export Hardware XSA
Fast Track
Next Step
References
Step 2: Create the Software Components and the Vitis DFX Platform
Step 2: Create the Software Components and the Vitis DFX Platform
Generating Device Tree
Add AI Engine Information to the system-user.dtsi File
Generate the Base Device Tree from the Static XSA
Creating the Vitis Platform
Prepare for Platform Packaging
Generating Static Boot Image
Platform Packaging
Next Step
Fast Track
Step 3: Test the Platform
Step 3: Test the Platform
Test 1: Read Platform Info
Test 2: Test PL kernels on the DFX platform
Create a Vector-Addition application
Test the Application on Hardware Emulation
Test the Application on Hardware
Test 3: Run an AI Engine + PL Acceleration Application Project
Create an AI Engine and PL System Design
Test the Application on Hardware Emulation
Test the Application on Hardware
Test the reconfiguration feature on hardware
What’s Next
Frequently Asked Questions
Frequently Asked Questions
SError Interrupt on xrt_cu_hls_init
ERROR: [BD 41-2666] NoC BDC Aperture Error: Dead-end Aperture
Create Vitis Platforms for Zynq UltraScale+ MPSoC
Step 1: Create Hardware Platform
Create the Base Vivado Project from Preset
Customize the System Design for Clock and Reset
Add Interrupt Support
Enable AXI Interfaces for the Platform
Emulation Setup (Optional)
Export Hardware XSA
Fast Track
Next Steps
Step 2: Create Vitis Software Platform
Prepare the Common Images
Create FSBL and PMU Firmware
Create the Device Tree File
Create a Vitis Platform
Fast Track
Next Steps
Step 3: Test the Platform
Test 1: Read Platform Info
Test 2: Run Vector Addition Application
Fast Track for Vector Addition
Test 3: Run a Vitis AI Demo
Known Issues
Congratulations
Custom Kria SOM Platform Creation Example
Step 1: Create the Vivado Hardware Design and Generate XSA
Create Base Vivado Project from Preset
Customize System Design for Clock and Reset
Add Interrupt Support
Enable AXI Interfaces for the Platform
Export Hardware XSA
Next Step
Step 2: Create the Vitis platform
Prepare the Common Image
Generate Software Components from the KV260 Starter Kit BSP(Optional)
Generate Device Tree Overlay
Create the Vitis Platform
Next Step
Step 3: Test the Platform
Test 1: Read Platform Info
Test 2: Run Vector Addition Application
Congratulations
Fast Track
Feature Tutorials
Incorporating Stream Interfaces
Kernel Modifications
1. Include necessary file headers.
2. Define the AXI stream data type and add the dds process function
3. Add more ports to the kernel functions
4. Add the declaration of the two ports
4. Add a piece of logic to call the dds process function
Host Modifications
1. Include necessary file headers.
2. Create a new cl_mem buffer
3. Bond the buffer with new arguments of the kernel
4. Map the new buffer to a pointer
5. Read data from DDR
6. Save the data into a file
7. Unmap the buffer object
PetaLinux Building and System Customization
Prepare the base platform
Create a PetaLinux Project
Customize Root File System, Kernel, Device Tree and U-boot
Update the Device tree
Add EXT4 rootfs support
Build PetaLinux Images
Fast Track

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