The v++ linker can automatically link the interrupt signals between kernel and platform. The available interrupt signals in the platform are exported by PFM.IRQ property.
For simple designs, interrupt signals can be sourced by processor’s pl_ps_irq. The limitation is that it can only supply maximum 16 interrupt signals. To supply more interrupt signals, you can use AXI Interrupt Controller. You will enable AXI HPM0 LPD to control the AXI Interrupt Controller, add the AXI Interrupt Controller and enable interrupt signals for PFM.IRQ.
Enable AXI HPM0 LPD to control the AXI Interrupt Controller
In the block diagram, double-click the Zynq UltraScale+ MPSoC block.
Select PS-PL Configuration > PS-PL interfaces > Master interface.
Enable the AXI HPM0 LPD option.
Expand the arrow before AXI HPM0 LPD. Check the AXI HPM0 LPD Data width settings and keep it as default 32.
Disable AXI HPM0 FPD and AXI HPM1 FPD
Click OK to finish the configuration.
Use AXI HPM0 LPD for controlling purpose. It would read and write 32-bit control registers. If the interface is more than 32, AXI Interconnect or SmartConnect will do AXI bus width conversion using PL logic. It would cost logic resource and introduce unnecessary latency.
Reserve AXI HPM0 FPD and AXI HPM1 FPD for kernel usage. Disabling them from the block diagram can prevent auto connection to use it by accident. You can export the unused AXI interfaces in Platform Setup, no matter it is visible in the block diagram or not.
Add the AXI Interrupt Controller and configure it.
Right-click Diagram view, and select Add IP, search and add AXI Interrupt Controller IP. It is instantiated as axi_intc_0.
Double-click the AXI Interrupt Controller block, change Interrupt Output Connection to Single so that it can be connected to PS IRQ interface.
Connect AXI Interfaces of
axi_intc_0to AXI HPM0 LPD of PS.
Click Run Connection Automation.
Review the settings (axi_intc_0 is enabled, s_axi Master interface is to be connect to /zynq_ultra_ps_e_0/M_AXI_HPM0_LPD).
Set Clock Source for Slave Interface and Clock Source for Master Interface to /clk_wiz_0/clk_out2(200 MHz).
NOTE: You wish interrupt controller and most kernel IRQ signals are synchronous to one clock. It is best for stability. But do not worry about the asynchronous IRQ if kernels are running at different clocks. The interrupt controller can manage asynchronous IRQ with level interrupt signals as well.
Connect irq of the Interrupt Controller
Connect axi_intc_0.irq to zynq_ultra_ps_e_0.pl_ps_irq[0:0]
The IPI design connection would like the following until now:
NOTE: If you have more than one
irqsignals to connect to
pl_ps_irqof PS, use a concat IP to concatenate them to a bus and then connect the bus to
Enable interrupt signals for the platform.
Go to the Platform Setup tab.
Go to the Interrupt tab.
Enable intr under axi_intc_0.