Customize System Design for Clock and Reset - 2023.2 English

Vitis Tutorials: Vitis Platform Creation

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2023.2 English

V++ linker can automatically link the clock signals between kernel and platform. The available clock signals in the platform are exported by PFM.CLK property.

For simple designs, interrupt signals can be sourced by processor’s pl_clk. The limitation is that the processor has maximum four pl_clks and their phase is not aligned.

To supply more interrupt signals, or to supply phase aligned clocks, you can use Clocking Wizard.

You will add the Clocking Wizard to the block diagram and enable clock signals for the platform.

  1. Add the clocking wizard block to generate three clocks:

    • Right-click Diagram view, and select Add IP.

    • Search for, and add a Clocking Wizard from the IP Search dialog.

    • Double-click the clk_wiz_0 IP block to open the Re-Customize IP dialog box.

    • Click the Output Clocks tab.

    • Enable clk_out1 through clk_out3 in the Output Clock column. Set the Requested Output Freq as follows:

      • clk_out1 to 100 MHz

      • clk_out2 to 200 MHz

      • clk_out3 to 400 MHz

    • At the bottom of the dialog box, set the Reset Type to Active Low.


    • Click OK to close the dialog.

    NOTE: Now you have set up the clock system for your design. This clock wizard uses the pl_clk as input clock and generates clocks needed for the whole logic design. In this straightforward design, you would use 100 MHz clock as the axi_lite control bus clock. 200 MHz and 400 MHz clocks are reserved for data-processing unit (DPU) AXI interface clock and DPU core clock during design linking phase. You are free to change the clock quantities and frequency to fit your target design. You will setup the clock export in future steps. First, you need to create reset signals for each clock because they are needed in clock export setup.

  2. Add three Processor System Reset blocks corresponding to the three clocks:

    • Right-click Diagram view, and select Add IP.

    • Search for and add a Processor System Reset from the IP Search dialog.

    • Rename the reset block to proc_sys_reset_1 so that it is easy to understand the relationship between reset modules and the clock signals.

    • Select the proc_sys_reset_1 block, type Ctrl-C and Ctrl-V to replicate two modules. They are named as proc_sys_reset_2 and proc_sys_reset_3 by default.

  3. Connect the clocks and resets:

    • Click Run Connection Automation, which will open a dialog that will help connect the proc_sys_reset blocks to the clocking wizard clock outputs.

    • Enable All Automation on the left side of the Run Connection Automation dialog box.

    • Select clk_in1 on clk_wiz_0, and set the Clock Source to /zynq_ultra_ps_e_0/pl_clk0.

    • For each proc_sys_reset instance, select the slowest_sync_clk, and set the Clock Source as follows:

      • proc_sys_reset_1 with /clk_wiz_0/clk_out1

      • proc_sys_reset_2 with /clk_wiz_0/clk_out2

      • proc_sys_reset_3 with /clk_wiz_0/clk_out3

    • On each proc_sys_reset instance, select the ext_reset_in, set Board Part Interface to Custom, and set the Select Manual Source to /zynq_ultra_ps_e_0/pl_resetn0.

    • Make sure all checkboxes are enabled, and click OK to close the dialog and create the connections.

    • Connect all the dcm_locked signals on each proc_sys_reset instance to the locked signal on clk_wiz_0.


  4. Enable clocks for the platform

    • Go to Platform Setup tab. If it is not opened yet, select Window -> Platform Setup to open it.

    • Click Clock tab

    • Enable all clocks under clk_wiz_0: clk_out1, clk_out2, clk_out3.

    • Change their ID to 0, 1 and 2.

    • Set a default clock: click Is Default for clk_out2.

    • After everything is setup, it should report Info: No problem with Clock interface.

      Platform Setup - Clock

    NOTE: There should be one and only one default clock in the platform. The v++ linker will use the default clock to connect the IP blocks if there are no user assignments for link configuration.