(Optional) Export block diagram Tcl to cross check the Tcl commands, or recreate design in the future.
Click File -> Export -> Export Block Diagram.
Check the Tcl file location, and click OK.
Open the exported tcl file
Go to the Platform Setup tab.
If the tab is not open, click menu Window -> Platform Setup to open it.
NOTE: If you cannot find Platform Setup tab, make sure your design is a Vitis platform project. Open Settings in Project Manager, go to Project Settings -> General tab, and make sure Project is an extensible Vitis platform is enabled.
Review the AXI port settings.
In axi_noc_ddr4, S01_AXI to S27_AXI are enabled. SP Tag is set to DDR.
NOTE: Vitis emulation automation scripts require that AXI slave interfaces on Versal platforms to have SP Tag as either DDR or LPDDR.
In icn_ctrl_0 and icn_ctrl_1, M01_AXI to M15_AXI are enabled. In icn_ctrl, M03_AXI and M04_AXI are enabled. Memport is set to M_AXI_GP. SP Tag is empty. These ports provide the AXI master interfaces to control PL kernels. In the block diagram, icn_ctrl_0 and icn_ctrl_1 connects to an AXI Verification IP because the AXI SmartConnect IP requires a load. The AXI Verification IP is used here as a dummy.
NOTE: SP Tag for AXI Master does not take effect.
Review the clock settings.
In Clock tab,
clk_outis the default clock. V++ linker will use this clock to connect the kernel if link configuration doesn’t specify any clocks.
The Proc Sys Reset property is set to the synchronous reset signal associated with each clock.
Review the Interrupt tab.
In Interrupt tab, intr is enabled.