Step 1: Create the Hardware Design - 2023.2 English

Vitis Tutorials: Vitis Platform Creation

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2023.2 English

This hardware design illustrates how to create a DFX hardware platform. You will use the AMD Versal™ DFX Extensible Embedded Example Design. You can extend the design to fulfill more complex requirements later.

The major differences between the AMD Vitis™ DFX platform and flat Vitis Platform is the AMD Vivado™ design. It needs to define the Block Design Container (BDC) for reconfigurable partition. BDC defines the dynamic region, or Reconfigurable Partition (RP).

Versal devices support partial reconfiguration for almost all component types. Refer to the Vivado Design Suite User Guide: Dynamic Function eXchange (UG909) for more details about the supported element types.

Here are some common practices for partitioning the IPs in Vitis platform designs.

IP Type Static Region Dynamic Region
AI Engine Y
Memory Memory Controller Export platform interfaces
Clock Y Y
Reset Y Y
Interrupt Interrupt Controller Export platform interfaces
AXI Master for IP Control Export platform interfaces
Decoupling for DFX DFX Decoupler Slice Registers when required
  • Control, Interface & Processing System (CIPS) must stay in the static region. The hard blocks in CIPS cannot be reconfigured.

  • AI Engine must stay in the dynamic region because it requires v++ to link to acceleration kernels during application development phase.

  • If the memory controllers are shared by the static region and the dynamic region (as shared by Arm® processors and acceleration kernels,), they should be instantiated to the static region.

  • Static region and dynamic region can have their own clock generator and reset logic. Dynamic region signals can be independent or derived from static region.

  • The Interrupt Controller should be instantiated in the static region because in order to avoid reloading the interrupt controller driver after DFX configuration. Interrupt signals and platform AXI interface signals can be exported from BDC.

  • The decoupling logics are required on the boundary between static region and dynamic region to help with timing closure and prevent metastability. XRT can turn on DFX Decoupler isolation mode before reconfiguration and turn off isolation after reconfiguration.

You will create the hardware design in Vivado first and then explain the details about the submodule in the CED DFX design.