- Overall Designs
The design of the Lepton Encoder is as follows:
The Lepton Encoder is composed of the following components:
AXI-to-Stream is responsible to load jpeg image from external memory into the FPGA.
Jpeg decode is responsible to decode the the jpeg data format into DCT coefficients.
IDCT is responsible to convert the DCT coefficients into pixels.
DC Predict is responsible to make prediction of DC coefficients. Pixels will be used in the dc prediction.
Line buffer implement a line buffer for the prediction of AC coefficients.
The Serialize and predict modules is responsible to do the prediction of AC coefficients.
The AC and DC coefficients and their predictions will be collected and then used to build up the probability tables.
Then Arithmetic Encode is used to generate the compressed bitstream.
The bitstream will be written to the external memory and moved back to the host to generate lepton file.