Vitis Cases Command Line Flow - 2023.2 English

Vitis Libraries

Release Date
2023-12-20
Version
2023.2 English

You can build the kernels and test the functionality through software emulation, hardware emulation, and running directly on a supported hardware with the FPGA.

  • Software emulation is equivalent to running a C-simulation of the kernel. The time for compilation is minimal and is therefore recommended to be the first step in testing the kernel.
  • Hardware emulation runs the test on the generated register transfer level (RTL) after synthesis of the C/C++ code. The simulation, since being done on RTL requires longer to complete when compared to software emulation.
  • To test on the hardware, the kernel must be compiled into a bitstream (building for hardware). This would consume some time since the C/C++ code must be converted to RTL, run through synthesis and implementation process before a bitstream is created. As a prerequisite the drivers has to be installed for corresponding XSA, for which the example was built for.

These modes, which are named sw_emu and hw_emu, allow the developer to profile and evaluate the performance of a design before compiling for board execution, which is named hw. It is recommended that all applications are executed in at least the sw_emu mode before being compiled and executed on an FPGA board.

where: sw_emu = software emulation, hw_emu = hardware emulation, hw = hardware