Xilinx LZ data compression architecture is targeted for FPGAs. It aims to provide high throughput. This architecture is developed and tested on Xilinx Alveo U200. Even though this architecture is designed for the LZ4 application, it is generic enough to support various other LZ based data compression algorithms like Snappy, LZ77 and LZO.
Xilinx FPGA based LZ data-compression architecture contains multiple compression engines which run concurrently to get higher throughput. Each compression engine is designed to process 1 byte/clock cycle @300MHz. If the design contains N compression engines, the overall throughput will be N x 300MB/s. For example, if you have 8 compression engines, then the overall throuput will be 8 x 300 = 2.4GB/s.
Note
This is a generic architecture to cover all the LZ based algorithms (LZ77, LZ4, LZO and Snappy).