AMD Vitis |trade| DSP Library offers a fully synthesizable Super Sample data Rate (SSR) FFT with a systolic architecture to process multiple input samples every clock cycle. The number of samples processed in parallel per cycle is denoted by the SSR factor. The SSR FFT is implemented as a C++ template function that synthesizes into a streaming architecture. The SSR FFT architecture used for implementation can be parameterized through template parameters, which are grouped in a C++ struct of type ssr_fft_default_params. A new structure can be defined by extending the default structure and re-defining required member constants as follows:
struct ssr_fft_fix_params:ssr_fft_default_params { static const int N = 1024; static const int R = 4; static const scaling_mode_enum scaling_mode = SSR_FFT_NO_SCALING; static const fft_output_order_enum output_data_order = SSR_FFT_NATURAL; static const int twiddle_table_word_length = 18; static const int twiddle_table_integer_part_length = 2; static const transform_direction_enum transform_direction = FORWARD_TRANSFORM; static const butterfly_rnd_mode_enum butterfly_rnd_mode = TRN; };
The structure above defines:
- N: Size or length of transform
- R: The number of samples to be processed in parallel SSR Factor and radix of SSR FFT algorithm used
- scaling_mode: The scaling mode as enumeration type (SSR FFT has three different scaling modes)
- output_data_order: Which will decided if data will be in natural order or digit reversed transposed order
- twiddle_table_word_length: Defines total number of bits to be used for storing twiddle table factors
- twiddle_table_integer_part_length: The number of integer bits used for storing integer part of twiddles
- transform_direction : Defines the direction of transform, inverse transform (SSR IFFT) or forward transform (SSR FFT)
- butterfly_rnd_mode : Defines the rounding mode used by butterflies in SSR FFT stages