The selection of input bit width depends on the input data characteristics and the required resolution, and is a data-dependent choice essentially depending on range and resolution of the test data. For simulation purposes, you can select an arbitrarily large number of bits for representing integer and fraction bits. For implementation, you must make an optimal choice keeping in mind the required SNR. The recommended strategy is to do the following:
- Keep the scaling mode fixed to SSR_FFT_NO_SCALING
- Change the input bits for integer and fraction representation by observing the signal to noise ratio at the output of 1-D SSR FFT
- Reduce the bit widths such that the output SNR requirement is met by the minimum required bits
Once the SNR requirements are met, you can proceed to other fixed point optimizations, such as bits required to store complex exponential tables and 1-D SSR FFT output scaling options.