You can change the number of bits used to quantize the sin/cos table (twiddle factors/complex exponential). The recommended setting is total 18 bits and 2 bits for the fraction. This setting ensures that during multiplication, the twiddle/sin/cos input can map to the 18-bit input of the DSP block in AMD Adaptive Engineering FPGAs. The model can synthesize and work for other large bit widths, but performance might be worse due to multiplication operations not mapping to a single DSP block and being implemented using multiple DSP blocks and/or FPGA fabric. The twiddle factor width reduction can be useful when the initial setting for twiddle factor storage is larger than 18 bits. By default, it is set to use 18 bits with 2 bits reserved for the signed integer part. The 2 bits are essentially needed to accurately represent a range of numbers from +1 to -1 (for sin/cos) in the table.