SSR_FFT_SCALE - 2023.2 English

Vitis Libraries

Release Date
2023-12-20
Version
2023.2 English

When you know that for a given 1-D FFT size N and SSR factor, the output will grow beyond a limit which DSP multiplier blocks cannot handle on a given FPGA device, you have the option to set the scaling on for every stage by selecting the SSR_FFT_SCALE option. This option scales the output in every stage by right shifting the output by log2 (SSR=R) in every stage. The recommended flow only provides a guideline for creating a fixed point model and discusses options available for it in 1-D SSR FFT. Depending on the design SNR/RMS requirements the user is required to carefully select all these parameters keeping in view different performance and SNR/RMS requirements for given application.