Implemention - 2023.2 English

The input matrix should ensure that the following conditions hold:

1. directed graph
2. No self edges
3. No duplicate edges
4. compressed sparse column (CSC) format

Note that this is not the “normalized” PageRank:

1. The results are the same as some third-party graph databases, ex. Tigergraph
2. The results are the same as some third-party graph databases after normalized of order 1, ex. Spark
3. In the current version, the weighted PageRank algorithm is implemented by default.
4. For the input unweighted graph, the user still needs to initialize the weight buffer manually to make the kernel work normally, as shown in the ./tests/host codes.

The algorithm implemention is shown as the figure below:

Figure 1 : PageRank calculate degree architecture on FPGA

Figure 2 : PageRank initiation module architecture on FPGA

Figure 3 : PageRank Adder architecture on FPGA

Figure 4 : PageRank calConvergence architecture on FPGA

As we can see from the figure:

1. Module calculate degree: first get the vertex node’s outdegree and keep them in one DDR buffer.
2. Module initiation: initiate PR DDR buffers and constant value buffer.
3. Module Adder: calculate Sparse matrix multiplification.
4. Module calConvergence: calculate convergence of pagerank iteration.