Profiling - 2023.2 English

Vitis Libraries

Release Date
2023-12-20
Version
2023.2 English

The hardware resources for 4x4 SVD are listed in Table 157. (Vivado result)

Table 157 Hardware resources for single 4x4 SVD
Engines BRAM DSP Register LUT Latency clock period(ns)
SVD 12 174 57380 38076 3051 3.029

The accuracy of SVD implementation has been verified with Lapack dgesvd (QR based SVD) and dgesvj (Jacobi SVD) functions. For a 2545-by-4 matrix, the relative error between our SVD and the two Lapack functions (dgesvd and dgesvj) is about \(1e^{-9}\)

Caution

The profiling resources differ a lot when choosing different chips. Here we use xcu250-figd2104-2L-e, with clock frequency 300MHz and the margin for clock uncertainty is set to 12.5%.