Bitwise AND - 2023.2 English

The bitwise_and function performs the bitwise AND operation for each pixel between two input images, and returns an output image.

Where,

is the intensity of output image at (x, y) position
is the intensity of first input image at (x, y) position
is the intensity of second input image at (x, y) position

API Syntax

template<int SRC_T, int ROWS, int COLS, int NPC=1, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_IN_2 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_1 = _XFCVDEPTH_DEFAULT>
void bitwise_and (
xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_1>& src1,
xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_2>& src2,
xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_OUT_1>& dst )

Parameter Descriptions

The following table describes the template and the function parameters.

Table 309 Table 41. bitwise_and Parameter Description
Parameter	Description
SRC_T	Input and output pixel type. Supports 1 channel and 3 channels (XF_8UC1,XF_16SC1,XF_16SC3 and XF_8UC3)
ROWS	Maximum height of input and output image.
COLS	Maximum width of input and output image (must be a multiple of 8, for 8 pixel mode)
NPC	Number of pixels to be processed per cycle; possible options are XF_NPPC1,XF_NPPC2,XF_NPPC4 and XF_NPPC8 for 1,2,4 pixel and 8 pixel operations respectively.
XFCVDEPTH_IN_1	Depth of the input image
XFCVDEPTH_IN_2	Depth of the input image
XFCVDEPTH_OUT_1	Depth of the output image
src1	Input image
src2	Input image
dst	Output image

Resource Utilization

The following table summarizes the resource utilization in different configurations, generated using Vivado HLS 2019.1 tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA, to process a grayscale HD (1080x1920) image.

Table 310 Table 42. bitwise_and Function Resource Utilization Summary
Operating Mode	Operating Frequency (MHz)	Utilization Estimate
Operating Mode	Operating Frequency (MHz)	BRAM_18K	DSP_48Es	FF	LUT	CLB
1 Pixel	300	0	0	62	44	10
8 Pixel	150	0	0	59	72	13

The following table summarizes the resource utilization in different configurations, generated using Vivado HLS 2019.1 tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA, to process a 4K 3Channel image.

Table 311 Table 43. bitwise_and Function Resource Utilization Summary
Operating Mode	Operating Frequency (MHz)	Utilization Estimate
Operating Mode	Operating Frequency (MHz)	BRAM_18K	DSP_48Es	FF	LUT	CLB
1 Pixel	300	0	1	155	61	22

Performance Estimate

The following table summarizes the performance in different configurations, as generated using Vivado HLS 2019.1 tool for the Xczu9eg-ffvb1156-1-i-es1, to process a grayscale HD (1080x1920) image.

Table 312 Table 44. bitwise_and Function Performance Estimate Summary
Operating Mode	Latency Estimate
Operating Mode	Max Latency (ms)
1 pixel operation (300 MHz)	6.9
8 pixel operation (150 MHz)	1.7