NV212NV12: - 2023.2 English

Vitis Libraries

Release Date
2023-12-20
Version
2023.2 English
template<int SRC_Y, int SRC_UV, int ROWS, int COLS, int NPC=1,int NPC_UV=1, int XFCVDEPTH_IN_0 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_IN_2 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_IN_3 = _XFCVDEPTH_DEFAULT>void nv212nv12(xf::cv::Mat<SRC_Y, ROWS, COLS, NPC, XFCVDEPTH_IN_0> & _y, xf::cv::Mat<SRC_UV, ROWS/2, COLS/2, NPC_UV, XFCVDEPTH_IN_1> & _uv, xf::cv::Mat<SRC_Y, ROWS, COLS, NPC, XFCVDEPTH_IN_2> & out_y, xf::cv::Mat<SRC_UV, ROWS/2, COLS/2, NPC_UV, XFCVDEPTH_IN_3> & out_uv)

Parameter Descriptions

The following table describes the template and the function parameters.

Table 442 Table Parameter Description
Parameter Description
SRC_Y Input Y pixel type. Only 8-bit, unsigned, 1-channel is supported (XF_8UC1)
SRC_UV Input UV pixel type. Only 8-bit, unsigned, 2-channel is supported (XF_8UC2)
ROWS Maximum height of input and output image
COLS Maximum width of input and output image. Must be multiple of N.
NPC_Y Number of Y pixels to be processed per cycle. Possible options are XF_NPPC1,XF_NPPC2,XF_NPPC4 and XF_NPPC8.
NPC_UV Number of UV Pixels to be processed per cycle. Possible options are XF_NPPC1,XF_NPPC2 and XF_NPPC4.
XFCVDEPTH_IN_0 Depth of input image
XFCVDEPTH_IN_1 Depth of input image
XFCVDEPTH_IN_2 Depth of input image
XFCVDEPTH_IN_3 Depth of input image
_y Y input image
_uv UV input image
out_y Y output image
out_uv UV output image

Resource Utilization

The following table summarizes the resource utilization of NV122NV21/NV212NV12 function in Normal mode (1-Pixel), as generated in the Vivado HLS 2019.1 tool for the Xilinx xczu9eg-ffvb1156-2-i-es2 FPGA to process a HD (1080x1920) image.

Operating Mode Operating Frequency (MHz) Utilization Estimate
BRAM_18K DSP_48Es FF LUT CLB
1 Pixel 300 0 0 258 161 61

Performance Estimate

The following table summarizes the performance of the kernel in single pixel configuration as generated using Vivado HLS 2019.1 tool for the Xilinx xczu9eg-ffvb1156-2-i-es2 FPGA to process a HD (1080x1920) image.

Table 443 Table Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz) 6.9