During a dilation operation, the current pixel intensity is replaced by the maximum value of the intensity in a nxn neighborhood of the current pixel.
API Syntax
template<int BORDER_TYPE, int TYPE, int ROWS, int COLS,int K_SHAPE,int K_ROWS,int K_COLS, int ITERATIONS, int NPC=1, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_1 = _XFCVDEPTH_DEFAULT>
void dilate (xf::cv::Mat<TYPE, ROWS, COLS, NPC, XFCVDEPTH_IN_1> & _src, xf::cv::Mat<TYPE, ROWS, COLS, NPC, XFCVDEPTH_OUT_1> & _dst,unsigned char _kernel[K_ROWS*K_COLS])
Parameter Descriptions
The following table describes the template and the function parameters.
| Parameter | Description |
|---|---|
| BORDER_TYPE | Border Type supported is XF_BORDER_CONSTANT |
| TYPE | Input and Output pixel type. Only 8-bit, unsigned, 1 and 3 channels are supported (XF_8UC1 and XF_8UC3) |
| ROWS | Maximum height of input and output image. |
| COLS | Maximum width of input and output image (must be multiple of 8, for 8-pixel operation) |
| K_SHAPE | Shape of the kernel . The supported kernel shapes are RECT, CROSS, and ELLIPSE. |
| NPC | Number of pixels to be processed per cycle; possible options are XF_NPPC1 and XF_NPPC8 for 1 pixel and 8 pixel operations respectively. |
| XFCVDEPTH_IN_1 | Depth of the input image. |
| XFCVDEPTH_OUT_1 | Depth of the output image. |
| K_ROWS | Height of the kernel. |
| K_COLS | Width of the kernel. |
| ITERATIONS | Number of times the dilation is applied. Currently supporting for Rectangular shape kernel element. |
| _src_mat | Input image |
| _dst_mat | Output image |
| _kernel | Dilation kernel of size K_ROWS * K_COLS. |
Resource Utilization
The following table summarizes the resource utilization of the Dilation function with rectangle shape structuring element in 1 pixel operation and 8 pixel operation, generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA for HD (1080X1920) image.
| Name | Resource Utilization | |
|---|---|---|
| 1 pixel per clock operation | 8 pixel per clock operation | |
| 300 MHz | 150 MHz | |
| BRAM_18K | 3 | 6 |
| DSP48E | 0 | 0 |
| FF | 411 | 657 |
| LUT | 392 | 1249 |
| CLB | 96 | 255 |
Performance Estimate
The following table summarizes the resource utilization of the Dilation function with rectangle shape structuring element in 1 pixel operation, generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA for 4K 3channel image.
| Name | Resource Utilization |
|---|---|
| 1 pixel per clock operation | |
| 300 MHz | |
| BRAM_18K | 18 |
| DSP48E | 0 |
| FF | 983 |
| LUT | 745 |
| CLB | 186 |
The following table summarizes a performance estimate of the Dilation function for Normal Operation (1 pixel) and Resource Optimized (8 pixel) configurations, generated using Vivado HLS 2019.1 tool for Xczu9eg-ffvb1156-1-i-es1 FPGA.
| Operating Mode | Latency Estimate | |
|---|---|---|
| Min Latency (ms) | Max Latency (ms) | |
| 1 pixel operation (300 MHz) | 7.0 | 7.0 |
| 8 pixel operation (150 MHz) | 1.87 | 1.87 |