The AddS function performs the addition operation between pixels of input image src and given scalar value scl and stores the result in dst.
dst(x,y)= src(x,y) + scl
Where (x,y) is the spatial coordinate of the pixel.
API Syntax
template<int POLICY_TYPE, int SRC_T, int ROWS, int COLS, int NPC =1, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_1 = _XFCVDEPTH_DEFAULT>
void addS(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_1> & _src1, unsigned char _scl[XF_CHANNELS(SRC_T,NPC)],xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_OUT_1> & _dst)
Parameter Descriptions
The following table describes the template and the function parameters.
| Parameter | Description |
|---|---|
| POLICY_TYPE | Type of overflow handling. It can be either, XF_CONVERT_POLICY_SATURATE or XF_CONVERT_POLICY_TRUNCATE. |
| SRC_T | Pixel type. Options are XF_8UC1, XF_8UC3, XF_16SC3 , and XF_16SC1. |
| ROWS | Maximum height of input and output image. |
| COLS | Maximum width of input and output image. In case of N-pixel parallelism, width should be multiple of N. |
| NPC | Number of pixels to be processed per cycle; possible options are XF_NPPC1 and XF_NPPC8 for 1 pixel and 8 pixel operations respectively. |
| XFCVDEPTH_IN_1 | Depth of input image |
| XFCVDEPTH_OUT_1 | Depth of output image |
| _src1 | First input image |
| _scl | Input scalar value, the size should be number of channels. |
| _dst | Output image |
Resource Utilization
The following table summarizes the resource utilization of the AddS function in both the resource optimized (8 pixel) mode and normal mode, as generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA.
| Name | Resource Utilization | |
|---|---|---|
| 1 pixel per clock operation | 8 pixel per clock operation | |
| 300 MHz | 150 MHz | |
| BRAM_18K | 0 | 0 |
| DSP48E | 0 | 0 |
| FF | 100 | 101 |
| LUT | 52 | 185 |
| CLB | 20 | 45 |
Performance Estimate
The following table summarizes a performance estimate of the kernel in different configurations, generated using Vivado HLS 2019.1 tool for Xczu9eg-ffvb1156-1-i-es1 FPGA to process a grayscale HD (1080x1920) image.
| Operating Mode | Latency Estimate |
|---|---|
| Max Latency (ms) | |
| 1 pixel operation (300 MHz) | 6.9 |
| 8 pixel operation (150 MHz) | 1.7 |