Extract Exposure Frames - 2023.2 English

The extractExposureFrames module returns the Shortexposureframe and Longexposureframe from the input frame using the Digital overlap parameter.

API Syntax

template <int SRC_T, int N_ROWS, int MAX_ROWS, int MAX_COLS, int NPPC = XF_NPPC1, int USE_URAM = 0, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_LEF = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_SEF = _XFCVDEPTH_DEFAULT>
         void extractExposureFrames(xf::cv::Mat<SRC_T, MAX_ROWS * 2, MAX_COLS, NPPC, XFCVDEPTH_IN_1>& _hdrSrc,
                                    xf::cv::Mat<SRC_T, MAX_ROWS, MAX_COLS, NPPC, XFCVDEPTH_LEF>& _lefSrc,
                                    xf::cv::Mat<SRC_T, MAX_ROWS, MAX_COLS, NPPC, XFCVDEPTH_SEF>& _sefSrc)

The following table describes the template and the function parameters.

Table 510 Table extractExposureFrames Parameter Description
Parameter	Description
SRC_T	Input and Output Pixel Type.
N_ROWS	Number of Digital overlap rows between SEF and LEF
N_COLS	Number of Digital overlap cols between SEF and LEF
MAX_ROWS	Maximum height of input and output image (Must be multiple of NPC)
MAX_COLS	Maximum width of input and output image (Must be multiple of NPC)
NPPC	Number of Pixels to be processed per cycle.
USE_URAM	enable to use URAM instead of BRAM in the design.
XFCVDEPTH_IN_1	Depth of the input image.
XFCVDEPTH_LEF	Depth of the output image.
XFCVDEPTH_SEF	Depth of the output image.
_hdrSrc	Input HDR image
_lefSrc	Long exposure frame
_sefSrc	Short exposure frame

Resource Utilization

The following table summarizes the resource utilization of the kernel in different configurations, generated using Vivado HLS 2019.2 tool for the Xilinx xc7vx485t-ffg1157-1 FPGA, to process a HD image.

Table 511 Table extractExposureFrames Resource Utilization Summary
Operating Mode	Operating Frequency (MHz)	Utilization Estimate
Operating Mode	Operating Frequency (MHz)	BRAM_18K	DSP_48Es	FF	LUT	CLB
1 pixel	300	8	0	408	304	120

Performance Estimate

The following table summarizes a performance estimate of the kernel in different configurations, as generated using Vivado HLS 2019.2 tool for the Xilinx xc7vx485t-ffg1157-1 FPGA, to process a HD image.

Table 512 Table extractExposureFrames Resource Utilization Summary
Operating Mode	Operating Frequency (MHz)	Latency Estimate
Operating Mode	Operating Frequency (MHz)	Max (ms)
1 pixel	300	14