Add Weighted - 2023.2 English

Vitis Libraries

Release Date
2023-12-20
Version
2023.2 English

The addweighted function calculates a weighted sum of two input images src1, src2 and generates the result in dst.

dst(x,y)= src1(x,y)*alpha+src2(x,y)*beta+ gamma

API Syntax

template< int SRC_T , int DST_T,   int ROWS, int COLS, int NPC=1, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_IN_2 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_1 = _XFCVDEPTH_DEFAULT>
void addWeighted(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_1> & _src1, float alpha, xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_2> & _src2, float beta, float gamma, xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_OUT_1> & _dst)

Parameter Descriptions

The following table describes the template and the function parameters.

Table 285 Table 29. Addweighted Parameter Description
Parameter Description
SRC_T Input Pixel Type. XF_8UC1,XF_8UC3 are supported
DST_T Output Pixel Type. XF_8UC1,XF_8UC3 are supported
ROWS Maximum height of input and output image
COLS Maximum width of input and output image. In case of N-pixel parallelism, width should be multiple of N
NPC Number of pixels to be processed per cycle; possible options are XF_NPPC1,XF_NPPC2,XF_NPPC4 and XF_NPPC8 for 1,2,4 pixel and 8 pixel operations respectively.
XFCVDEPTH_IN_1 Depth of the input image
XFCVDEPTH_IN_2 Depth of the input image
XFCVDEPTH_OUT_1 Depth of the output image
_src1 First input image
Alpha Weight applied on first image
_src2 Second Input image
Beta Weight applied on second image
gamma Scalar added to each sum
_dst Output image

Resource Utilization

The following table summarizes the resource utilization of the Addweighted function in Resource optimized (8 pixel) mode and normal mode, as generated in Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA.

Table 286 Table 30. Addweighted Function Resource Utilization Summary
Name Resource Utilization
1 pixel per clock operation 8 pixel per clock operation
300 MHz 150 MHz
BRAM_18K 0 0
DSP48E 11 25
FF 903 680
LUT 851 1077
CLB 187 229

Performance Estimate

The following table summarizes a performance estimate of the kernel in different configurations, generated using Vivado HLS 2019.1 tool for Xczu9eg-ffvb1156-1-i-es1 FPGA to process a grayscale HD (1080x1920) image.

Table 287 Table 31. Addweighted Function Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz) 6.9
8 pixel operation (150 MHz) 1.7