Histogram Computation - 2023.2 English

Vitis Libraries
Release Date
2023-12-20
Version
2023.2 English
The calcHist function computes the histogram of given input image.
image83
Where, H is the array of 256 elements.

API Syntax

template<int SRC_T,int ROWS, int COLS,int NPC=1, int XFCVDEPTH_IN = _XFCVDEPTH_DEFAULT>
void calcHist(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN> & _src, uint32_t *histogram)

Parameter Descriptions

The following table describes the template and the function parameters.

Table 577 Table . calcHist Parameter Description
Parameter Description
SRC_T Input pixel type. Only 8-bit, unsigned, 1 and 3 channels are supported (XF_8UC1 and XF_8UC3)
ROWS Maximum height of input and output image.
COLS Maximum width of input and output image (must be multiple of 8, for 8-pixel operation)
NPC Number of pixels to be processed per cycle XF_NPPC1 XF_NPPC8 are supported
XFCVDEPTH_IN Depth of the input image.
_src Input image
histogram Output array of 256 elements

Resource Utilization

The following table summarizes the resource utilization of the calcHist function for Normal Operation (1 pixel) and Resource Optimized (8 pixel) configurations, generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA at 300 MHz for 1 pixel case and at 150 MHz for 8 pixel mode.

Table 578 Table . calcHist Function Resource Utilization Summary
Name Resource Utilization
Normal Operation (1 pixel) Resource Optimized (8 pixel)
BRAM_18K 2 16
DSP48E 0 0
FF 196 274
LUT 240 912
CLB 57 231

The following table summarizes the resource utilization of the calcHist function for Normal Operation (1 pixel), generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA at 300 MHz for 1 pixel case for 4K image 3 channel.

Table 579 Table . calcHist Function Resource Utilization Summary
Name Resource Utilization
Normal Operation (1 pixel)
BRAM_18K 8
DSP48E 0
FF 381
LUT 614
CLB 134

Performance Estimate

The following table summarizes a performance estimate of the calcHist function for Normal Operation (1 pixel) and Resource Optimized (8 pixel) configurations, generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA at 300 MHz for 1 pixel and 150 MHz for 8 pixel mode.

Table 580 Table . calcHist Function Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz) 6.9
8 pixel operation (150 MHz) 1.7