InRange - 2023.2 English

Vitis Libraries

Release Date
2023-12-20
Version
2023.2 English

The InRange function checks if pixels in the image src lie between the given boundaries. dst(x,y) is set to 255, if src(x,y) is within the specified thresholds and otherwise 0.

Dst(I)= lowerb ≤ src(I) ≤ upperb

Where (x,y) is the spatial coordinate of the pixel.

API Syntax

template<int SRC_T, int ROWS, int COLS,int NPC=1, int XFCVDEPTH_IN = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT = _XFCVDEPTH_DEFAULT>
void inRange(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN> & src,unsigned char lower_thresh,unsigned char upper_thresh,xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_OUT> & dst)

Parameter Descriptions

The following table describes the template and the function parameters.

Table 603 Table . InRange Parameter Description
Parameter Description
SRC_T Input Pixel Type. 8-bit, unsigned, 1 and 3 channels are supported (XF_8UC1 and XF_8UC3).
ROWS Maximum height of input and output image.
COLS Maximum width of input and output image. In case of N-pixel parallelism, width should be multiple of N.
NPC Number of pixels to be processed per cycle; possible options are XF_NPPC1 and XF_NPPC8 for 1 pixel and 8 pixel operations respectively.
XFCVDEPTH_IN Depth of the input image.
XFCVDEPTH_OUT Depth of the output image.
src Input image
dst Output image
lower_thresh Lower threshold value
upper_thresh Upper threshold value

Resource Utilization

The following table summarizes the resource utilization of the InRange function in Resource optimized (8 pixel) mode and normal mode as generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA

Table 604 Table . InRange Function Resource Utilization Summary
Name Resource Utilization
1 pixel per clock operation 8 pixel per clock operation
300 MHz 150 MHz
BRAM_18K 0 0
DSP48E 0 0
FF 86 154
LUT 60 148
CLB 15 37

Performance Estimate

The following table summarizes a performance estimate of the kernel in different configurations, generated using Vivado HLS 2019.1 tool for Xczu9eg-ffvb1156-1-i-es1 FPGA to process a grayscale HD (1080x1920) image.

Table 605 Table . InRange Function Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz) 6.9
8 pixel operation (150 MHz) 1.7