Set - 2023.2 English

Vitis Libraries

Release Date
2023-12-20
Version
2023.2 English

The Set function sets the each pixel in input image to a given scalar value and stores the result in dst.

API Syntax

template< int SRC_T , int ROWS, int COLS, int NPC=1, int XFCVDEPTH_IN_1 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_1 = _XFCVDEPTH_DEFAULT>
void set(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN_1> & _src1, unsigned char _scl[XF_CHANNELS(SRC_T,NPC)], xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_OUT_1> & _dst)

Parameter Descriptions

The following table describes the template and the function parameters.

Table 710 Table . Set Parameter Description
Parameter Description
SRC_T Input pixel type. 8-bit, unsigned 1 and 3 channels are supported (XF_8UC1,XF_8UC3).
ROWS Maximum height of input and output image
COLS Maximum width of input and output image. Must be multiple of 8, for 8-pixel operation.
NPC Number of pixels to be processed per cycle XF_NPPC1 XF_NPPC8 are supported
XFCVDEPTH_IN_1 Depth of the input image.
XFCVDEPTH_OUT_1 Depth of the output image.
_src1 First input image
_scl Scalar value
_dst Output image

Resource Utilization

The following table summarizes the resource utilization of the Set function in Resource optimized (8 pixel) mode and normal mode as generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA.

Table 711 Table . Set Function Resource Utilization Summary
Name Resource Utilization
1 pixel per clock operation 8 pixel per clock operation
300 MHz 150 MHz
BRAM_18K 0 0
DSP48E 0 0
FF 87 87
LUT 43 42
CLB 17 18

Performance Estimate

The following table summarizes a performance estimate of the kernel in different configurations, generated using Vivado HLS 2019.1 tool for Xczu9eg-ffvb1156-1-i-es1 FPGA to process a grayscale HD (1080x1920) image.

Table 712 Table . Set Function Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz) 6.9
8 pixel operation (150 MHz) 1.7