ISP all_in_one_adas pipeline - 2023.2 English

void ISPPipeline_accel(ap_uint<INPUT_PTR_WIDTH>* img_inp,                 /* Array2xfMat */
                       ap_uint<OUTPUT_PTR_WIDTH>* img_out,                /* xfMat2Array */
                       ap_uint<OUTPUT_PTR_WIDTH>* img_out_ir,             /* xfMat2Array */
                       int height,                                        /* HDR, rgbir2bayer, fifo_copy */
                       int width,                                         /* HDR, rgbir2bayer, fifo_copy */
                       short* wr_hls,                                     /* HDR */
                       uint16_t rgain,                                    /* gaincontrol */
                       uint16_t bgain,                                    /* gaincontrol */
                       char *R_IR_C1_wgts,                                /* rgbir2bayer */
                       char *R_IR_C2_wgts,                                /* rgbir2bayer */
                       char *B_at_R_wgts,                                 /* rgbir2bayer */
                       char *IR_at_R_wgts,                                /* rgbir2bayer */
                       char *IR_at_B_wgts,                                /* rgbir2bayer */
                       char *sub_wgts,                                    /* rgbir2bayer */
                       uint16_t pawb,                                     /* awb */
                       int blk_height,                                    /* LTM */
                       int blk_width,                                     /* LTM */
                       float c1,                                          /* gtm */
                       float c2,                                          /* gtm */
                       unsigned char gamma_lut[256 * 3],                  /* gammacorrection */
                       unsigned short mode_reg,
                       ap_uint<INPUT_PTR_WIDTH>* lut,                     /* lut3d */
                       int lutDim                                         /* lut3d */ ){
// clang-format off
#pragma HLS INTERFACE m_axi port=img_inp          offset=slave bundle=gmem1
#pragma HLS INTERFACE m_axi port=img_out          offset=slave bundle=gmem2
#pragma HLS INTERFACE m_axi port=img_out_ir       offset=slave bundle=gmem3
#pragma HLS INTERFACE m_axi port=R_IR_C1_wgts     offset=slave bundle=gmem4
#pragma HLS INTERFACE m_axi port=R_IR_C2_wgts     offset=slave bundle=gmem4
#pragma HLS INTERFACE m_axi port=B_at_R_wgts      offset=slave bundle=gmem4
#pragma HLS INTERFACE m_axi port=IR_at_R_wgts     offset=slave bundle=gmem4
#pragma HLS INTERFACE m_axi port=IR_at_B_wgts     offset=slave bundle=gmem4
#pragma HLS INTERFACE m_axi port=sub_wgts         offset=slave bundle=gmem5
#pragma HLS INTERFACE m_axi port=gamma_lut        offset=slave bundle=gmem6
#pragma HLS INTERFACE m_axi port=wr_hls           offset=slave bundle=gmem7
#pragma HLS INTERFACE m_axi port=lut              offset=slave bundle=gmem8

#pragma HLS ARRAY_PARTITION variable=IR_at_B_wgts complete dim=1
#pragma HLS ARRAY_PARTITION variable=bgain        complete dim=1
#pragma HLS ARRAY_PARTITION variable=rgain        complete dim=1
#pragma HLS ARRAY_PARTITION variable=R_IR_C2_wgts complete dim=1
#pragma HLS ARRAY_PARTITION variable=R_IR_C1_wgts complete dim=1
#pragma HLS ARRAY_PARTITION variable=sub_wgts     complete dim=1
#pragma HLS ARRAY_PARTITION variable=IR_at_R_wgts complete dim=1
#pragma HLS ARRAY_PARTITION variable=mode_reg     complete dim=1
#pragma HLS ARRAY_PARTITION variable=pawb         complete dim=1
#pragma HLS ARRAY_PARTITION variable=hist0_awb    complete dim=1
#pragma HLS ARRAY_PARTITION variable=hist1_awb    complete dim=1

#pragma HLS ARRAY_PARTITION variable=omin dim=1   complete
#pragma HLS ARRAY_PARTITION variable=omin dim=2   cyclic factor=2
#pragma HLS ARRAY_PARTITION variable=omin dim=3   cyclic factor=2
#pragma HLS ARRAY_PARTITION variable=omax dim=1   complete
#pragma HLS ARRAY_PARTITION variable=omax dim=2   cyclic factor=2
#pragma HLS ARRAY_PARTITION variable=omax dim=3   cyclic factor=2
// clang-format on
if (!flag) {
    ISPpipeline(img_inp, img_out, img_out_ir, mode_reg, height, width, wr_hls, R_IR_C1_wgts, R_IR_C2_wgts,
                B_at_R_wgts, IR_at_R_wgts, IR_at_B_wgts, sub_wgts, rgain, bgain,  hist0_awb, hist1_awb,
                igain_0, igain_1, pawb, gamma_lut, omin[0], omax[0], omin[1], omax[1], blk_height,blk_width,
                mean2, mean1, L_max2, L_max1, L_min2, L_min1, c1, c2, lut, lutDim);
     flag = 1;
    } else {
    ISPpipeline(img_inp, img_out, img_out_ir, mode_reg, height, width, wr_hls, R_IR_C1_wgts, R_IR_C2_wgts,
                B_at_R_wgts, IR_at_R_wgts, IR_at_B_wgts, sub_wgts, rgain, bgain,  hist1_awb, hist0_awb,
                igain_1, igain_0, pawb, gamma_lut, omin[1], omax[1], omin[0], omax[0], blk_height, blk_width,
                mean1, mean2, L_max1, L_max2, L_min1, L_min2, c1, c2, lut, lutDim);
    flag = 0;
    }
}

    // Create a kernel:
    OCL_CHECK(err, cl::Kernel kernel(program, "ISPPipeline_accel", &err));

    for (int i = 0; i < 3; i++) {
    OCL_CHECK(err, q.enqueueWriteBuffer(buffer_inVec,                 // buffer on the FPGA
                                        CL_TRUE,                      // blocking call
                                        0,                            // buffer offset in bytes
                                        vec_in_size_bytes,            // Size in bytes
                                        gamma_lut));

    OCL_CHECK(err, q.enqueueWriteBuffer(buffer_R_IR_C1,               // buffer on the FPGA
                                        CL_TRUE,                      // blocking call
                                        0,                            // buffer offset in bytes
                                        filter1_in_size_bytes,        // Size in bytes
                                        R_IR_C1_wgts));

    OCL_CHECK(err, q.enqueueWriteBuffer(buffer_R_IR_C2,               // buffer on the FPGA
                                        CL_TRUE,                      // blocking call
                                        0,                            // buffer offset in bytes
                                        filter1_in_size_bytes,        // Size in bytes
                                        R_IR_C2_wgts));

    OCL_CHECK(err, q.enqueueWriteBuffer(buffer_B_at_R,                // buffer on the FPGA
                                        CL_TRUE,                      // blocking call
                                        0,                            // buffer offset in bytes
                                        filter1_in_size_bytes,        // Size in bytes
                                        B_at_R_wgts));

    OCL_CHECK(err, q.enqueueWriteBuffer(buffer_IR_at_R,               // buffer on the FPGA
                                        CL_TRUE,                      // blocking call
                                        0,                            // buffer offset in bytes
                                        filter2_in_size_bytes,        // Size in bytes
                                        IR_at_R_wgts));

    OCL_CHECK(err, q.enqueueWriteBuffer(buffer_IR_at_B,               // buffer on the FPGA
                                        CL_TRUE,                      // blocking call
                                        0,                            // buffer offset in bytes
                                        filter2_in_size_bytes,        // Size in bytes
                                        IR_at_B_wgts));

    OCL_CHECK(err, q.enqueueWriteBuffer(buffer_sub_wgts,              // buffer on the FPGA
                                        CL_TRUE,                      // blocking call
                                        0,                            // buffer offset in bytes
                                        sub_wgts_in_size_bytes,       // Size in bytes
                                        sub_wgts));

    if (hdr_en) {
        OCL_CHECK(err, q.enqueueWriteBuffer(buffer_inVec_Weights,     // buffer on the FPGA
                                            CL_TRUE,                  // blocking call
                                            0,                        // buffer offset in bytes
                                            vec_weight_size_bytes,    // Size in bytes
                                            wr_hls));

        OCL_CHECK(err, q.enqueueWriteBuffer(imageToDevice,
                                            CL_TRUE, 0,
                                            image_in_size_bytes,
                                            interleaved_img.data));

    } else {
        OCL_CHECK(err, q.enqueueWriteBuffer(imageToDevice,
                                            CL_TRUE, 0,
                                            image_in_size_bytes,
                                            in_img1.data));
    }
    OCL_CHECK(err, q.enqueueWriteBuffer(buffer_inLut,                 // buffer on the FPGA
                                        CL_TRUE,                      // blocking call
                                        0,                            // buffer offset in bytes
                                        lut_in_size_bytes,            // Size in bytes
                                        casted_lut,                   // Pointer to the data to copy
                                        nullptr));
    // Profiling Objects
    cl_ulong start = 0;
    cl_ulong end = 0;
    double diff_prof = 0.0f;
    cl::Event event_sp;

    // Launch the kernel

    OCL_CHECK(err, err = q.enqueueTask(kernel, NULL, &event_sp));

    clWaitForEvents(1, (const cl_event*)&event_sp);

    event_sp.getProfilingInfo(CL_PROFILING_COMMAND_START, &start);

    event_sp.getProfilingInfo(CL_PROFILING_COMMAND_END, &end);

    diff_prof = end - start;
    std::cout << (diff_prof / 1000000) << "ms" << std::endl;
    // Copying Device result data to Host memory
    q.enqueueReadBuffer(imageFromDevice, CL_TRUE, 0, image_out_size_bytes, out_img.data);
    if (rgbir_en) {
        q.enqueueReadBuffer(imageFromDevice_ir, CL_TRUE, 0, image_out_ir_size_bytes, out_img_ir.data);
    }
}