Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)

Zynq UltraScale+ MPSoC ZCU106 Video Codec Unit Targeted Reference Design User Guide (UG1250)
Introduction
About this TRD
Zynq UltraScale+ MPSoC Overview
Reference Design Overview
Key Features
Targeted Reference Design Details
Design Modules
Multi-Stream Audio Design
Full-fledged VCU TRD
PL DDR HDR10 HDMI Video Capture and Display
LLP2 PS DDR NV12 HDMI Video Capture and HDMI Display
LLP2 PL DDR HDMI Video Capture and HDMI Display
LLP2 PL DDR HLG SDI Video Capture and Display
VCU TRD YUV444 Video Capture and Display
Design Components
APU
PL
APU Software Platform
Introduction
Software Architecture
Video
Driver Architecture
Media Framework
Graphics
Display
Accelerator
Audio
Software Stack
GUI Application (vcu_qt)
Number of Inputs
Input Options
Codec
SCD
Preset
Output Options
Demo Mode
Settings
Record
Stream Out
Audio Setting
Monitor Options
GStreamer Application (vcu_gst_app)
GStreamer Interface Library (vcu_gst_lib)
Description
VCU Encoder/Decoder Features
Multi-Stream
Video Buffer Management
AXI Performance Monitor (APM) Library (vcu_apm_lib)
Video Library (vcu_video_lib)
Query Display Configurations
Media Pipeline Configuration
System Considerations
Boot Process
Global Address Map
Memory
Video Buffer Format
Hardware Platform
Introduction
Capture/Input Pipelines
Processing Pipelines
Display/Output Pipelines
Clocking
Reset
Video Pipelines
TPG Capture Pipeline
HDMI RX Capture Pipeline
MIPI CSI-2 RX Capture Pipeline
SDI RX Capture Pipeline
DP TX Display Pipeline
HDMI TX Display Pipeline
SDI TX Display Pipeline
HDMI Audio RX Pipeline
HDMI Audio TX Pipeline
SCD Design Pipeline
I2S Audio Pipeline
VCU DDR4 Controller Pipeline
Low Latency Pipeline
Address Map
Interrupt Map
Input Configuration File
Descriptions
Additional Resources and Legal Notices
Finding Additional Documentation
Documentation Portal
Documentation Navigator
Design Hubs
Support Resources
References
Revision History
Please Read: Important Legal Notices

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