1.1 Building the PL Design

Zynq UltraScale plus MPSoC Power Management

Release Date
  • Install the Vivado Tools as described here .
  • Note: The 2017.1 version requires the SDx version of the tools.
  • Note: Please refer to C:\zynqus\pwr\hw\readme.txt for any additional instructions.
  • Windows > All Programs > Xilinx Design Tools > Vivado 2016.2 > Vivado 2016.2 > File > Open Project > File name: C:\zynqus\pwr\hw\zcu102_ecc\zcu102.xpr > OK
  • Tcl Console > get_board_parts
  • Program and Debug (at bottom of menu) > Generate Bitstream
  • Note: If you modify the PL design and need to export a new psu_init.tcl file, prior to 2016.4, you will need to manually modify it to support the DisplayPort feature. This can be done by copying C:\zynqus\pwr\sw\zu_processor_gpio_wrapper_hw_platform_0\location\psu_init.tcl to C:\zynqus\pwr\sw\psu_init_new.tcl, and commenting out the line "mask_poll 0xFD4023E4 0x00000010". If you do not, the SDK R5 debugger will not run.