1.2 Running the PL Design from the JTAG Debugger

Zynq UltraScale plus MPSoC Power Management

Release Date
2022-07-26
  • Set Mode SW6 to On-On-On-On, and power cycle the ZCU102 board.
  • After Building the PL Design: Program and Debug > Open Hardware Manager > No hardware target is open. Open target > Auto Connect > There are no debug cores. Program device > xczu9eg_0 > Program