1.2 Running the R5 Design from the JTAG Debugger

Zynq UltraScale plus MPSoC Power Management

Release Date
2022-07-26
  • Plug Micro USB cable in to USB JTAG Port J2.
  • Set the Boot Mode Switch (SW6) 1-4 On-On-On-On (JTAG Boot) and reboot the ZCU102.
  • Windows > All Programs > Xilinx Design Tools > SDK 2016.2 > Workspace: C:\zynqus\pwr\sw > Right Click r5 > Debug As > Launch on Hardware (System Debugger)
  • Note: If you changed the PL design, and now the R5 debugger does not work, please see the Note in the previous PL page , section 1.1.