Adding Power and Clock controls in FSBL

Zynq UltraScale plus MPSoC Power Management

Release Date
2022-07-26

For applications that don't use EEMI, the easy way to power down and clock gate unused blocks is by adding the control code into FSBL hooks. This technique will work for most of the use-cases.

The example code below can be customized to power down the unused blocks at FSBL post psu_init stage in xfsbl_hooks.c:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 #define ZU_PMU_PWRDN_STATUS 0xFFD80210 #define ZU_PMU_PWRDN_INT_EN 0xFFD80218 #define ZU_PMU_PWRDN_TRIG 0xFFD80220 #define ZU_BIT(n) (1U << (n)) #define ZU_PWRDN_ACPU1_MASK ZU_BIT(1) #define ZU_PWRDN_ACPU2_MASK ZU_BIT(2) #define ZU_PWRDN_ACPU3_MASK ZU_BIT(3) #define ZU_PWRDN_PP0_MASK ZU_BIT(4) #define ZU_PWRDN_PP1_MASK ZU_BIT(5) #define ZU_PWRDN_RPU_MASK ZU_BIT(10) #define ZU_PWRDN_TCM0A_MASK ZU_BIT(12) #define ZU_PWRDN_TCM0B_MASK ZU_BIT(13) #define ZU_PWRDN_TCM1A_MASK ZU_BIT(14) #define ZU_PWRDN_TCM1B_MASK ZU_BIT(15) #define ZU_PWRDN_USB0_MASK ZU_BIT(20) #define ZU_PWRDN_USB1_MASK ZU_BIT(21) static void ZU_PowerDown(u32 IslandMask) { Xil_Out32(ZU_PMU_PWRDN_INT_EN, IslandMask); Xil_Out32(ZU_PMU_PWRDN_TRIG, IslandMask); /* Loop until all power down reqs are served */ while((Xil_In32(ZU_PMU_PWRDN_STATUS)) != 0); } /*** Add below code at the end of XFsbl_HookPsuInit */ ZU_PowerDown(ZU_PWRDN_ACPU1_MASK); ZU_PowerDown(ZU_PWRDN_ACPU2_MASK); ZU_PowerDown(ZU_PWRDN_ACPU3_MASK); ZU_PowerDown(ZU_PWRDN_PP0_MASK); ZU_PowerDown(ZU_PWRDN_PP1_MASK); ZU_PowerDown(ZU_PWRDN_RPU_MASK); ZU_PowerDown(ZU_PWRDN_TCM0A_MASK); ZU_PowerDown(ZU_PWRDN_TCM0B_MASK); ZU_PowerDown(ZU_PWRDN_TCM1A_MASK); ZU_PowerDown(ZU_PWRDN_TCM1B_MASK); ZU_PowerDown(ZU_PWRDN_USB0_MASK); ZU_PowerDown(ZU_PWRDN_USB1_MASK);