Inspect Clocks and Resets

Zynq UltraScale plus MPSoC Power Management

Release Date
2022-07-26

Clock control registers are present in CRL_APB and CRF_APB and can be used to examine the current states of peripheral clocks. Some clocks are active by default at reset and so might be ungated and resulting in unnecessary power consumption. To get a list of all clocks that are active at reset can be found by examining the CLK_ACT bit in *_REF_CTRL registers in CRF_APB and CRL_APB registers. Refer to https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html

For example, DP_VIDEO clock is active at reset. So, it might be causing some unnecessary power drain even if the DP is not used and held in reset.

Here are the xsdb commands to inspect clocks and resets:

1 2 3 4 5 6 targets -set -filter {name =~ "PSU"} # LPD clocks and Resets rrd crl_apb #FPD clocks and Resets rrd crf_apb