PL Static Power

Zynq UltraScale plus MPSoC Power Management

Release Date

PL doesn’t have power gating provisions like PS to control static power in unused parts of the logic. The only way to control static power is to control the voltage level. The option of using low power variants (-L) is attractive for users who have “low power” as a main design goal. Refer to “Device Selection” section for details.

Over that, there are some specific techniques which allow users to reduce the PL voltage and put it into retention state when there is no activity.