Schematic Design

Zynq UltraScale plus MPSoC Power Management

Release Date
2022-07-26

To achieve low power states involving turning off PL/FPD domains and features like board power off from software, there are certain guidelines that need to be followed. These are dealt in detail on the page: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1417183259 .

An optimized schematic design can sometimes save 15% more power by enabling a low power standby state, or by allowing a more aggressive PL Power Management design.