- Refer to UG1137 "Zynq UltraScale+ MPSoC Software Developer Guide" Chapter 9 for more information about power management APIs.
- See here on how to generate the Config Object file.
- Refer to UG1209 "Zynq UltraScale+ MPSoC: Embedded Design Tutorial" for more details.
- Google "Xilinx UGXXXX" to find the latest version of the Xilinx document.
The Zynq UltraScale+ MPSoC controls the external power supplies to the Full Power Domain and the Programmable Logic Domain via the GPI1 and GPI1 signals. These signals must be mapped to their MIO pins in Vivado PCW. See TRM chapter on "Platform Management Unit" for details.