Using PS->PL Clocks

Zynq UltraScale plus MPSoC Power Management

Release Date
2022-07-26

There are four PS to PL clocks available to be used as clock sources for IPs in the PL. These clocks are similar to PS peripheral clocks and have controls like clock gating, dividers and PLL source section. They are modeled in PMUFW and can be controlled via EEMI clock control APIs.

Here is a screenshot of PS-PL clock controls in Vivado PCW Wizard:

Here are the node IDs for these PS->PL clocks:

1 2 3 4 5 6 7 #define PM_CLOCK_PL0_REF                     71U #define PM_CLOCK_PL1_REF                     72U #define PM_CLOCK_PL2_REF                     73U #define PM_CLOCK_PL3_REF                     74U

These clocks can be controlled using clock management APIs in Linux similar to other PS clocks. PL IP drivers can configure these clocks as clock sources in device-tree and can manage these clocks at runtime. FCLK driver available in Xilinx Linux tree can be taken as reference for such drivers. Currently FCLK driver requests and holds these clock active.

Here is an example on exercising these clock APIs from Linux DebugFS interface:

1 2 3 4 5 6 7 8 # Get the current clock gate state echo pm_clock_getstate 71 >/sys/kernel/debug/zynqmp-firmware/pm # Disable/Gate the clock echo pm_clock_disable 71 >/sys/kernel/debug/zynqmp-firmware/pm # Enable/Ungate the clock echo pm_clock_enable 71 >/sys/kernel/debug/zynqmp-firmware/pm

A more detailed explanation of clock control debugfs interface is provided in Linux PM wiki.