After Turning on a Reference Clock to the LCPLL/RPLL Being Used

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

If the reference clock(s) changes or transceiver(s) are powered up after configuration, perform a full RX sequential reset after the PLL fully completes its reset procedure.