Enabling the RX Asynchronous Gearbox

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID

AM002

Release Date

2023-10-26

Revision

1.3 English

The following table describes the attribute settings to enable the RX asynchronous gearbox.

Table 1. Enabling the RX Asynchronous Gearbox
Attribute	Label	Description
CH*_RX_PCS_CFG2[5]	USE_GB	This bit must be set to `1'b1`.
CH*_RX_PCS_CFG2[4:0]	MODE	Bit[4] - Must be set to `1'b1`. Bit[3] - Reserved. Must be set to `1'b0`. Bit[2] - Reserved. Must be set to `1'b0`. Bit[1] - Reserved. Must be set to `1'b0`. Bit[0] - Set to `1'b1` to use 64B/66B gearbox when using the asynchronous gearbox.