Eye Scan Architecture

The blocks shaded gray in the figure below describe the portion of the PMA architecture that supports eye scan. The horizontal offset (HORZ_OFFSET) advances or delays the sampling time of the offset samples relative to the data samples. The vertical offset (VERT_OFFSET) raises or lowers the differential voltage threshold to which the equalized waveform is compared. The data samples are deserialized into the Rdata bus, and the offset samples are deserialized into the Sdata bus.

When in DFE mode (CH*_RXLPMEN=0), due to the unrolled first DFE tap, two separate eye scan measurements are needed, one at +UT and one at –UT, to measure the TOTAL BER at a given vertical and horizontal offset.

The figure below describes the portion of the PCS architecture that supports eye scan. The 80-bit Rdata bus contains the data samples, and each bit of the 80-bit Sdata bus is one if and only if the corresponding data sample and offset sample are not equal. (See ES_ERRDET_EN in Table 2.)

In the figure above, the sample counter and error counter count the total number of bits examined and the total number of errors observed. (The sample count is scaled by ES_PRESCALE and int_datawidth. See Figure 4 and Figure 5.) The state machine controls the recording of Rdata and Sdata values in the FIFOs and the accumulation of counts in the sample counter and error counter. The functions of the various blocks in the above figure are as follows.

• The FIFOs retain the two most recent cycles (a maximum of 160 bits) of Rdata and Sdata. This data serves the following purposes:
  • Support detection of errors by examination of Sdata.
  • Support detection of desired data patterns by examination of Rdata.
  • Provide data snapshots for external examination. The state machine might stop operation of the FIFOs under certain conditions, after which the FIFO contents can be read out to interconnect logic via the APB3 interface.
• The count qualifier compares the Rdata FIFO contents against ES_QUALIFIER. Its output goes High to indicate a match, which enables the sample counter (via the prescaler) and the error counter to advance. High ES_QUAL_MASK bits omit selected bits of Rdata from the comparison. If all the bits are High, no bits of Rdata have to match, which means operation of the counters is always enabled. Setting some ES_QUAL_MASK bits Low inhibits counter operation unless the corresponding bits of Rdata match the specified pattern in ES_QUALIFIER. The count qualifier output is High if the condition (Rdata_FIFO[k] EQUALS ES_QUALIFIER[k]) OR ES_QUAL_MASK[k] is satisfied for every k in the range 0 to 159. For a statistical eye view, ES_QUAL_MASK is set to {160{1’b1}}. For a waveform view, some ES_QUAL_MASK bits can be set to 0 to constrain counter operation or to define a trigger for capturing Rdata and Sdata for examination.
• The prescaler receives the count qualifier output signal and passes some sub-multiple of High values to the sample counter so that each increment of the sample counter corresponds to some multiple number of High outputs received from the count qualifier. ES_PRESCALE defines the number of High count qualifier outputs indicated by each sample counter increment, 2^{ES_PRESCALE+1}, in the range 2 to 4,294,967,296.
• The sample counter counts the total number of cycles (scaled by ES_PRESCALE) in which counting of bit errors is enabled by the count qualifier.
• The error counter accumulates an error count over time. Counting the total number of bit errors for a statistical eye view requires setting ES_SDATA_MASK[159:80] = {80{1’b1}}. For this usage, the error counter counts the total number of bit errors (1-bits) in Sdata[79:0]. High ES_SDATA_MASK bits can omit selected bits of Sdata from being checked. Commonly, a statistical eye view uses ES_SDATA_MASK[159:0] = {80{1’b1}, 80{1’b0}} for 80-bit data (see the RX Margin Analysis Attributes table). Error bits in Sdata[159:80] are not counted because Sdata[159:80] contains the previous value of Sdata[79:0] that was counted in the previous cycle. The number of bit errors counted in a given cycle is the number of values of k in the range 0 to 79 for which the condition Sdata_FIFO[k] AND NOT ES_SDATA_MASK[k] is satisfied.

  For other usages of eye scan data (such as waveform view), exactly one bit of ES_SDATA_MASK[159:0] is set to 0. The error counter counts the number of errors in Rdata_FIFO[k] (i.e., Sdata_FIFO[k] = 1) for the bit k with ES_SDATA_MASK[k] = 0. Alternatively, if ES_ERRDET_EN is FALSE, the error counter counts the total number of times the offset data Sdata_FIFO[k] is 1, regardless of whether or not this is the erroneous value. If exactly one bit of ES_SDATA_MASK[159:0] is 0, or if at least one bit of ES_SDATA_MASK[159:80] is 0, then the error counter increments by 1 if the count qualifier output is High and the condition Sdata_FIFO[k] AND NOT ES_SDATA_MASK[k] is satisfied for any k in the range 0 to 159. If any bit of ES_SDATA_MASK[159:80] is 0, then error counter increments only by 1, and not by the total number of bit errors that might otherwise be detected within a single cycle.

• The state machine controls the operation of the eye scan block to count errors or to capture snapshots of interest for Rdata and Sdata. It has two modes of operation, Run and Arm:
  • Run mode (the left loop in the figure below) supports statistical data collection for statistical eye, waveform, and scope views. It initiates operation of the sample counter and error counter as described above, stopping the operation when either the sample counter or the error counter saturates (reaches its maximum value), or when a APB3 operation terminates Run mode.
  • Arm mode (the right loop in the figure below) supports the capture of Rdata and Sdata snapshots (by disabling further FIFO operation) that can be read out through the APB3 interface. Arm mode can be used, for example, to determine data patterns that are prone to causing poor eye margin. These patterns can then drive generation of waveform views for further analysis. The state machine can be configured to stop Rdata and Sdata FIFO operation in these cases:
    • An error occurs (anywhere in Sdata_FIFO[159:0], subject to masking by ES_SDATA_MASK[159:0]).
    • Rdata matches a specified pattern (defined by ES_QUALIFIER and ES_QUAL_MASK).
    • Interconnect input EYESCANTRIGGER causes a trigger by going High.
    • A trigger is forced via an attribute write to ES_CONTROL.

The following figure documents the state transitions in the eye scan state machine.

ES_CONTROL[1:0] are the signals arm and run, respectively. From the WAIT state, run initiates the BER measurement loop (left) and arm starts the diagnostic loop (right).

The RESET state zeros the error and sample counters, then enters the COUNT state or the ARMED state (depending on whether run or arm is active).

In the COUNT state, samples and errors are accumulated in the counters. When either counter is saturated, both counters stop and transition to the END state. This transition to the END state is detected by polling es_control_status[3:0]. Bit 0 (done) is set active only in the END, READ, and WAIT states. Bits [3:1] display the current state of the state machine.

The END state transitions to the WAIT state when run is set back to zero. The es_sample_count[15:0] and es_error_count[15:0] can be read either in the END or WAIT state.

In LPM mode, the BER is calculated as:

In DFE mode, two error accumulations are required, one with EYESCAN_VS_UT_SIGN = 0 and one with EYESCAN_VS_UT_SIGN = 1. The bit error ratio is then calculated as:

To maintain resolution and repeatability of these error accumulations for “deep” BER values, ES_PRESCALE must be adjusted dynamically between accumulations, balancing the need for good repeatability against the desire to not take any longer than needed. That is, 1 or 2 errors on one accumulation might be 0 or 3 or 5 errors on a repeated accumulation, changing BER significantly. But 30 errors on one accumulation changing to 27 or 35 errors on another accumulation does not change BER significantly. The following table shows the required maximum ES_PRESCALE to confirm a given BER with a given bus width.

In the ARMED state, the FIFOs (successive cycles of Rdata and of Sdata) are stopped when a trigger event occurs. The trigger event is either the count qualifier pulse, the logical OR of all bits into the error counter, or a manual trigger provided from a APB3 data input or from a port. One of these four options is selected by trig[3:0] = ES_CONTROL[5:2].

In the READ state, the last two cycles of Rdata can be read from the APB3 read-only register, es_rdata[159:0], and the last two cycles of Sdata can be read from the APB3 read-only register, es_sdata[159:0].