The fabric configuration interface (APB3) allows the user to dynamically update the attributes of the GTYE5_QUAD or GTYP_QUAD primitives. The APB3 interface is a processor-friendly synchronous interface with an address bus (APB3PADDR) and separated data buses for reading (APB3PRDATA) and writing (APB3PWDATA) configuration data to the primitive. An enable signal (APB3PENABLE), a read/write signal (APB3PWRITE), and a ready/valid signal (APB3PREADY) are the control signals that implement read and write operations, indicate operation completion, or indicate the availability of data. The Versal Adaptive SoC Transceivers Wizard must be used because it includes additional logic to hold the APB3PADDR for three cycles.