The LCPLL must be reset before it can be used. Each transceiver Quad has dedicated reset ports for each of the two respective LCPLLs. As shown in the figure, LCPLLRESET is an input that resets LCPLL. LCPLLLOCK is an output that indicates the reset process is done. The guideline for this asynchronous LCPLLRESET pulse width is one period of the reference clock. After an LCPLLRESET pulse, the internal reset controller generates an internal LCPLL reset followed by an internal SDM reset. The time required for LCPLL to lock is affected by a few factors, such as bandwidth setting and clock frequency.
Figure 1. LCPLL Reset Timing Diagram
