OBUFDS_GTE5_ADV

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

The reference clock output mode structure with the OBUFDS_GTE5_ADV primitive is shown in the following figure. The ports and attributes controlling the reference clock output are tied to the OBUFDS_GTE5_ADV software primitives. The port RXRECCLKSEL controls the multiplexer that selects between HSCLK*_RXRECCLKOUT[0/1] from the four different channels in a Quad.

Figure 1. Reference Clock Output Use Model with OBUFDS_GTE5_ADV