Ports and Attributes

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

The following table defines the RX asynchronous gearbox ports.

Table 1. RXASYNCGEARBOX Ports
Port Direction Clock Domain Description
CH[0/1/2/3]_RXGEARBOXSLIP Input RXUSRCLK

When asserted, this port causes the gearbox contents to slip to the next possible alignment. This port is used to achieve proper data alignment within interconnect Port RXDATA and RXHEADER.

Asserting this port for one RXUSRCLK cycle changes the data alignment coming out of the gearbox.

RXGEARBOXSLIP must be deasserted for at least one cycle and then reasserted to cause a new realignment of the data. If multiple realignments occur in rapid succession, it is possible to pass the proper alignment point without recognizing the correct alignment point in the interconnect logic.

CH[0/1/2/3]_RXHEADER[5:0] Output RXUSRCLK

RXHEADER[1:0]: Header output in normal mode.

RXHEADER[4:3]: Header output with 16-byte RXDATA interface.

RXHEADER[2] and [5] are used in 64B/67B gearbox

CH[0/1/2/3]_RXHEADERVALID[1:0] Output RXUSRCLK

Indicates if RXHEADER is valid.

RXHEADERVALID[0]: 1'b1 indicates that RXHEADER is valid for current data. When using an 8-byte RX data interface (RX_DATA_WIDTH = 64) or 16-byte RX data interface (RX_DATA_WIDTH = 128), RXHEADERVALID[0] always outputs 1'b1 indicating RXHEADER is valid for every RXUSRCLK cycle. RXHEADERVALID[0] toggles every RXUSRCLK cycle when using a 4-byte RX data interface.

RXHEADERVALID[1]: When using a 16-byte RX data interface RXHEADERVALID[1] always outputs 1'b1 indicating a second header. RXHEADERVALID[1] toggles every RXUSRCLK cycle when using a 4-byte RX data interface.

CH[0/1/2/3]_RXLATCLK Input CLOCK Input port used to provide a clock for the RX asynchronous gearbox latency calculation.

The following table defines the RX asynchronous gearbox attributes.

Table 2. RXASYNCGEARBOX Attributes
RXASYNCGEARBOX Attributes
Attribute Address
CH0_RXGBOX_FIFO_LATENCY 0x086d
CH1_RXGBOX_FIFO_LATENCY 0x096d
CH2_RXGBOX_FIFO_LATENCY 0x0a6d
CH3_RXGBOX_FIFO_LATENCY 0x0b6d
Label Bit Field Description
RXGBOX_FIFO_LATENCY [29:16]

Measured latency in UI through the RX asynchronous gearbox averaged over SAMPLE_PERIOD (CH*_RX_PCS_CFG2[12:10]) cycles. The reported latency is in units of 1/8 UI.

The RXGBOX_FIFO_LATENCY is read-only.

 
Attribute Address
CH0_RXGBOX_FIFO_OVERFLOW 0x086d
CH1_RXGBOX_FIFO_OVERFLOW 0x096d
CH2_RXGBOX_FIFO_OVERFLOW 0x0a6d
CH3_RXGBOX_FIFO_OVERFLOW 0x0b6d
Label Bit Field Description
RXGBOX_FIFO_OVERFLOW [31:31]

RX asynchronous gearbox FIFO overflow status. A High indicates that overflow error has occured.

The RXGBOX_FIFO_OVERFLOW is read-only.

 
Attribute Address
CH0_RXGBOX_FIFO_UNDERFLOW 0x086d
CH1_RXGBOX_FIFO_UNDERFLOW 0x096d
CH2_RXGBOX_FIFO_UNDERFLOW 0x0a6d
CH3_RXGBOX_FIFO_UNDERFLOW 0x0b6d
Label Bit Field Description
RXGBOX_FIFO_UNDERFLOW [30:30]

RX asynchronous gearbox FIFO underflow status. A High indicates that underflow error has occured.

The RXGBOX_FIFO_UNDERFLOW is read-only.

 
Attribute Address
CH0_RX_PCS_CFG2 0x0C67
CH1_RX_PCS_CFG2 0x0D67
CH2_RX_PCS_CFG2 0x0E67
CH3_RX_PCS_CFG2 0x0F67
Label Bit Field Description
SAMPLE_PERIOD [12:10]

Number of CH*_RXLATCLK cycles over which averaging take place for latency calculation:

3'b000: 256

3'b001: 512

3'b010: 1024

3'b011: 2048

3'b100: 4096

3'b101: 8192

3'b110: 16384

3'b111: 32768

USE_GB [5:5] This attribute must be set to 1'b1 to enable either the RX synchronous or asynchronous gearbox.
MODE [4:0]

This attribute indicates the RX gearbox modes:

Bit[4]:

1'b0 = Select Synchronous Gearbox.

1'b1 = Select Asynchronous Gearbox.

Bit[3]:

Reserved. Set to 1'b0.

Bit[2]:

Reserved. Set to 1'b0.

Bit[1]:

Reserved. Set to 1'b0.

Bit[0]:

1'b0 = 64B/67B gearbox mode for Interlaken (Only valid for synchronous gearbox)

1'b1 = 64B/66B.