RX Initialization and Reset

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

The transceiver RX uses a reset state machine to control the reset process. Due to its complexity, the transceiver RX is partitioned into more reset regions than the transceiver TX. The partition allows RX initialization and reset to be operated in either sequential mode, as shown in the following figure, or single mode:

  1. RX in Sequential Mode: To initialize the transceiver RX, RXRESETMODE must be set to sequential mode. The RX components that are required to be rest are determined by setting the appropriate RXPMARESETMASK and RXPCSRESETMASK bits to High. The reset sequence is then triggered by toggling GTRXRESET and then internal component resets are triggered sequentially. The reset state machine executes the reset sequence as shown in the following figure, covering the entire RX PMA, RX DPI, RX buffer bypass (if used), and RX PCS. During normal operation, the reset state machine runs until RXRESETDONE transitions from Low to High.
  2. RX in Single Mode: When the transceiver RX is in single mode, RXRESETMODE must be set to single mode. The RX components that are required to be rest are determined by setting the appropriate RXPMARESETMASK and RXPCSRESETMASK bits to High. The reset sequence is then triggered by toggling GTRXRESET and the internal component resets are triggered simultaneously. In addition, EYESCANRESET, RXOOBRESET, RXCDRRESET, RXPRBSCNTRESET and HSDPPCSRESET pins are available to reset those components directly in single mode. RXRESETDONE does not assert in single mode.

In either sequential mode or single mode, the RX reset state machine does not reset the PCS until RXUSERRDY goes High. Drive RXUSERRDY High after all clocks used by the application, including RXUSRCLK, are shown to be stable.

Figure 1. Transceiver RX Reset State Machine Sequence