Rate Change Use Mode with Reference Clock Changes

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

If the user decides to use a different reference clock, whether it is an entirely different clock source or the same clock source but with only changes in the actual frequency, additional steps need to be followed when performing the rate change.

If the user decides to use a different reference clock port/source, the current reference clock source must be kept unchanged and stable during the entire rate change sequence. At the same time, the new reference clock source should be set and stable when the rate change procedure starts. The following timing diagram shows the required sequence.

Figure 1. Transceiver Rate Change with Changes in REFCLK Source

If the user decide to use the same reference clock source but the actual frequency will change, the corresponding GPI ports need to be toggled according to the following timing diagram below. The new reference clock frequency should be set and stable when the GPI port is toggled. See the following timing diagram for the proper rate change sequence under this use mode.

Figure 2. Transceiver Rate Change with Changes in REFCLK Frequency without Port Change