In single-lane with asynchronous gearbox mode, the TXUSRCLK domain is used to drive logic in the TXPHYCLK domain. When the TX internal data width is identical to the fabric interface data width, the TX buffer is directly bypassed, and clock phase compensation is provided by the asynchronous gearbox FIFO. In this mode, the latency is deterministic and the asynchronous gearbox FIFO can provide measured latency. For more details on how to read the asynchronous gearbox FIFO latency, refer to TX Asynchronous Gearbox.
Use these transceiver settings to bypass the TX buffer with asynchronous gearbox enabled in single-lane 1:1 mode:
- CH*_TX_PCS_CFG0[5] =
1'b1(USE_BG) - CH*_TX_PHALIGN_CFG0[31] =
1'b0(DLY_ALIGN_EN) - CH*_TX_PHALIGN_CFG0[30] =
1'b0(PH_ALIGN_EN) - CH*_TX_PHALIGN_CFG0[17:16] =
2'b00(SYNC_MODE) - CH*_TX_PHALIGN_CFG0[15] =
1'b0(SYNC_MULTI_LANE) - CH*_TX_PHALIGN_CFG0[14] =
1'b1(TXBUF_BYPASS_MODE) - CH*_TX_PHALIGN_CFG1[2:1] =
2'b00(CHAIN_MODE) - CH*_TX_PHALIGN_CFG1[0] =
1'b1(ASYNC_GBOX_PHALIGN_EN) - CH*_PIPE_CTRL_CFG7[2:0] =
3'b011or3'b101(TXOUTCLKCTL) to select either the transceiver reference clock or the programmable divider clock as the source of TXOUTCLK
In this particular use mode, because the asynchronous gearbox FIFO provides the phase compensation, there is no need to perform the TX phase alignment procedure as shown in Figure 1.