TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Single-Lane Auto Mode with TX Master

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)
Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

Use these transceiver settings to bypass the TX and RX buffer in single-lane mode with a common clock, TX master.

Common clock settings:

  • CH*_RX_PHALIGN_CFG5[27:26] = 2'b01 (CMN_FAB_CLK_PHALIGN_MODE)

TX buffer bypass settings:

  • CH*_TX_PHALIGN_CFG0[31] = 1'b1 (DLY_ALIGN_EN)
  • CH*_TX_PHALIGN_CFG0[30] = 1'b1 (PH_ALIGN_EN)
  • CH*_TX_PHALIGN_CFG0[17:16] = 2'b00 (SYNC_MODE)
  • CH*_TX_PHALIGN_CFG0[15] = 1'b0 (SYNC_MULTI_LANE)
  • CH*_TX_PHALIGN_CFG0[14] = 1'b1 (TXBUF_BYPASS_MODE)
  • CH*_TX_PHALIGN_CFG1[2:1] = 2'b00 (CHAIN_MODE)
  • CH*_TX_PHALIGN_CFG1[0] = 1'b0 (ASYNC_GBOX_PHALIGN_EN)
  • CH*_PIPE_CTRL_CFG7[2:0] = 3'b011 or 3'b101 (TXOUTCLKCTL) to select either the transceiver reference clock or the programmable divider clock as the source of TXOUTCLK.

RX buffer bypass settings:

  • CH*_RX_PHALIGN_CFG0[31] = 1'b1 (DLY_ALIGN_EN)
  • CH*_RX_PHALIGN_CFG0[30] = 1'b1 (PH_ALIGN_EN)
  • CH*_RX_PHALIGN_CFG0[17:16] = 2'b00 (SYNC_MODE)
  • CH*_RX_PHALIGN_CFG0[15] = 1'b0 (SYNC_MULTI_LANE)
  • CH*_RX_PHALIGN_CFG0[14] = 1'b1 (RXBUF_BYPASS_MODE)
  • CH*_RX_PHALIGN_CFG1[3:2] = 2'b00 (CHAIN_MODE)
  • CH*_RX_PHALIGN_CFG1[1] = 1'b0 (ASYNC_GBOX_PHALIGN_EN)

The following figure shows an example of a single-lane common clock buffer bypass with a TX master.

Figure 1. Common Clock Buffer Bypass Lanes in Single-Lane TX Master Mode

The following figure shows the port connection for a single-lane common clock buffer bypass with a TX master.

Figure 2. Port Connection for Common Clock Buffer Bypass Lanes in Single-Lane TX Master Mode

The following timing diagram shows the required steps to perform common clock phase and delay alignment in single-lane TX master mode.

Figure 3. Common Clock Buffer Bypass—Single-Lane TX Master Mode

Notes relevant to the figure:

  1. The sequence of events in the figure is not drawn to scale.
  2. After conditions such as a reset or rate change, common clock phase alignment must be performed. The common clock phase and delay alignments are initiated by asserting CH*_TXPHDLYRESET and CH*_RXPHDLYRESET.
  3. Common clock phase alignment with TX master is done when the rising edge of CH*_TXSYNCDONE is detected. This signal should remain asserted until another alignment procedure is initiated.
  4. An assertion/deassertion of GTTXRESET and GTRXRESET is required if CH*_TXSYNCDONE does not follow the sequence shown in the figure.
  5. TX delay alignment continues to adjust TXUSRCLK to compensate for temperature and voltage variations.