There is one resistor calibration circuit (RCAL) shared between all transceiver Quad primitives in a transceiver Quad column. The MGTAVTTRCAL and MGTRREF pins connect the bias circuit power and the external calibration resistor to the RCAL circuit. The RCAL circuit performs the resistor calibration only during configuration of the Versal adaptive SoC. Prior to configuration, all analog supply voltages must be present and within the proper tolerance as specified in the Versal device data sheets. If an entire power supply group (PSG) is not used by any Quads, MGTAVTTRCAL and MGTRREF should be tied to ground. See Analog Power Supply Pins for more details regarding RCAL biasing recommendations when there are unused Quads.
The RCAL circuit is associated with the GTY or GTYP transceiver Quad that is the RCAL master. The RCAL master performs the termination resistor calibration during configuration of the Versal adaptive SoC and then distributes the calibrated values to all of the GTY or GTYP transceiver Quads in the column. The Quad in which the RCAL circuit is located must be powered on.
Connect the MGTAVTTRCAL pin to the GTY_AVTT supply and to a pin on the 100Ω precision external resistor. The other pin of the resistor is connected to the MGTRREF pin. The resistor calibration circuit provides a controlled current load to the resistor connected to the MGTRREF pin. It then senses the voltage drop across the external calibration resistor and uses that value to adjust the internal resistor calibration setting. The quality of the resistor calibration is dependent on the accuracy of the voltage measurement at the MGTAVTTRCAL and MGTRREF pins. To eliminate errors due to the voltage drop across the traces that lead from the resistor and to the Versal device pins, the trace from the MGTAVTTRCAL pin to the resistor should have the same length and geometry as the trace that connects the other pin of the resistor to the MGTRREF pin. Also, the maximum DC resistance of the PCB trace must be limited to less than 0.5Ω. See the suggested layout in the following figure.
