Asynchronous MUX Using BUFGCTRL

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

In some cases an application requires immediate switching between clock inputs or bypassing the edge sensitivity of BUFGCTRL. An example is when one of the clock inputs is no longer switching. If this happens, the clock output would not have the proper switching conditions because the BUFGCTRL never detected a clock edge. This case uses the asynchronous MUX. The following figure illustrates an asynchronous MUX with BUFGCTRL design example.

Figure 1. Asynchronous MUX using BUFGCTRL Design Example

The following figure shows the asynchronous MUX timing diagram.

Figure 2. Asynchronous MUX Timing Diagram
The figure shows:
  • The current clock is from I0.
  • S is activated High.
  • The clock output immediately switches to I1.
  • When ignore signals are asserted High, glitch protection is disabled.