BUFGCE Clock Buffers

Versal ACAP Clocking Resources Architecture Manual (AM003)

Document ID
AM003
Release Date
2022-05-24
Revision
1.4 English

BUFGCE is a clock buffer with one clock input, one clock output, and a clock enable line (see the following figure). This buffer provides glitch less clock gating. BUFGCE can directly drive the routing resources and is a clock buffer with a single gated input. Its O output is 0 when CE is Low (inactive). When CE is High, the I input is transferred to the O output.

Figure 1. BUFGCE with CE

The following table shows the BUFGCE attributes.

Table 1. BUFGCE Attributes
Attribute Name Values Default Type Description
CE_TYPE SYNC, ASYNC, HARDSYNC SYNC STRING Sets the clock enable behavior where SYNC allows for glitchless transition while ASYNC allows immediate transition. The SYNC setting times the CE pin in the Vivado tools while the ASYNC setting ignores the timing arc. HARDSYNC turns ON an internal 3-stage synchronizer for maximum performance. However, that results in a latency of either three or four clock cycles.
STARTUP_SYNC FALSE, TRUE FALSE STRING Defines whether logic to CE input is staged
Note: For additional tool related attributes used by Vivado Design Suite during the opt_design stage, refer to the Versal Architecture AI Core Series Libraries Guide (UG1353).

The following figure shows the BUFGCE timing diagram.

Figure 2. BUFGCE Timing Diagram